1. Field of the Disclosure
Embodiments of the present disclosure relate to a semiconductor memory device, and more particularly to a multi-bit non-volatile memory (NVM) device, a method of operating the same, and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices can be broadly store data in a hard disc and classified as either volatile or non-volatile memory. In order to perform fast data processing when power is being turned on, a volatile memory such as DRAM is employed in an apparatus such as a computer.
However, instead of the DRAM typically used for computers, the growing market for mobile phones and digital cameras has created a demand for non-volatile memory with fast processing speed which can store data regardless of whether power is interrupted.
Flash memory is a widely used type of non-volatile memory device, with a storage node structure for storing electric charge. Two common forms of flash memory are the floating gate type and the SONOS type with an oxide/nitride/oxide (ONO) structure. Hereinafter, a conventional SONOS type non-volatile memory device will be described with reference to FIG. 1.
Referring to FIG. 1, a SONOS type non-volatile memory device uses a nitride layer 120 as a storage node. An oxide layer 115 for tunneling charge or injecting hot carriers is located between the nitride layer 120 and a semiconductor substrate 105.
A blocking insulating film, e.g., a silicon oxide layer, 125 is formed between the nitride layer 120 and a control gate electrode 130. By this construction, the nitride layer 120 as the storage node is separated from the semiconductor substrate 105 and the control gate electrode 130 by the oxide layers 115 and 125. Accordingly, once charge is stored in the nitride layer 120, it can be maintained even if the power supply is cut off.
In this structure, programming is performed to store charge in the nitride layer 120 by supplying a program voltage to the control gate electrode 130. By doing so, the electrons accelerated in source and drain regions 110 are energized and then injected into the nitride layer 120. This method is hot carrier injecting.
Otherwise, the electrons of the semiconductor substrate 105 may be injected into the nitride layer 120 by tunneling, in accordance with a voltage supplied to the control gate electrode 130.
Erasing the charge from the nitride layer 120 is performed by supplying a negative voltage to the control gate electrode 130, or supplying a positive voltage to the semiconductor substrate 105. At this time, the charge stored in the nitride layer 120 is erased by tunneling.
A multi-bit SONOS type non-volatile memory is currently under development. This device utilizes the local pinning of charges stored in the nitride layer 120. That is, when opposite electric fields are applied to both ends of the source and drain regions 110, electrons can be separately stored in both ends of the nitride layer 120.
However, multi-bit operation using the single nitride layer 120 has a problem in that the two different stored charges cannot be distinguished as a gate length is decreased. Moreover, the mixing of the stored charge cannot be completely prevented.